//OK! RST is reset for reg1, but not influence on reg2.
  always @(posedge CLK ) begin
    if(RST) begin
      reg1 <= 8'd0;
    end else begin
      reg1 <= 8'd0;
      reg2 <= 8'd1;
    end
  end

  //Illegal! RST is regard as clock signal for reg2 by verilog simulator.
  always @(posedge CLK or posedge RST) begin
    if(RST) begin
      reg1 <= 8'd0;
    end else begin
      reg1 <= 8'd0;
      reg2 <= 8'd1;
    end
  end